View ISL6609IBZ_6284089.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn9221.1 isl6609, isl6609a synchronous rectified mosfet driver the isl6609, isl6609a is a hi gh frequency, mosfet driver optimized to drive two n-channel power mosfets in a synchronous-rectified buck converter topology. this driver combined with an intersil isl63xx or isl65xx multiphase pwm controller forms a complete single-stage core-voltage regulator solution with high efficiency performance at high switching frequency for ad vanced microprocessors. the ic is biased by a single low voltage supply (5v), minimizing driver switching losses in high mosfet gate capacitance and high switching frequency applications. each driver is capable of driving a 3nf load with less than 10ns rise/fall time. bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective n-channel mosfets. adaptive shoot-throu gh protection is integrated to prevent both mosfets from conducting simultaneously. the isl6609, isl6609a features 4a typical sink current for the lower gate driver, enhancing the lower mosfet gate hold-down cap ability during phase node rising edge, preventing power loss caused by the self turn-on of the lower mosfet due to the high dv/dt of the switching node. the isl6609, isl6609a also features an input that recognizes a high-impedance state, working together with intersil multiphase pwm controllers to prevent negative transients on the controlled output voltage when operation is suspended. this feature eliminat es the need for the schottky diode that may be utilized in a power system to protect the load from negative output volt age damage. in addition, the isl6609a?s bootstrap function is designed to prevent the boot capacitor from overchar ging, should excessively large negative swings occur at the transitions of the phase node. features ? drives two n-channel mosfets ? adaptive shoot-through protection ?0.4 ? on-resistance and 4a sink current capability ? supports high switching frequency - fast output rise and fall - ultra low three-state hold-off time (20ns) ? isl6605 replacement wit h enhanced performance ? boot capacitor overchar ge prevention (isl6609a) ?low v f internal bootstrap diode ? low bias supply current ? enable input and power-on reset ? qfn package - compliant to jedec pub95 mo-220 qfn-quad flat no leads-product outline - near chip-scale package footprint; improves pcb efficiency and thinner in profile ? pb-free plus anneal available (rohs compliant) applications ? core voltage supplies for intel? and amd? microprocessors ? high frequency low profile high efficiency dc/dc converters ? high current low voltage dc/dc converters ? synchronous rectification for isolated power supplies related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)? data sheet march 6, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006. all rights reserved. intel? is a registered trademark of intel corporation. amd? is a registered trademark of advanced micro devices, inc. all other trademarks mentioned are the property of their respective owners.
2 fn9221.1 march 6, 2006 pinouts ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6609cbz isl6609cbz 0 to 70 8 ld soic m8.15 isl6609crz 609z 0 to 70 8 ld 3x3 qfn l8.3x3 ISL6609IBZ ISL6609IBZ -40 to 85 8 ld soic m8.15 isl6609irz 09iz -40 to 85 8 ld 3x3 qfn l8.3x3 isl6609acbz 6609acbz 0 to 70 8 ld soic m8.15 isl6609acrz 09az 0 to 70 8 ld 3x3 qfn l8.3x3 isl6609aibz 6609aibz -40 to 85 8 ld soic m8.15 isl6609airz 9aiz -40 to 85 8 ld 3x3 qfn l8.3x3 add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl6609, isl6609a (soic) top view isl6609, isl6609a (qfn) top view block diagram isl6609 and isl6609a ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase en vcc lgate 7 ugate phase 8 4 3 1 2 6 gnd lgate en vcc boot pwm 5 6 vcc pwm vcc 4.25k 4k control logic shoot- through protection boot ugate phase lgate gnd vcc en r boot integrated 3 ? resistor (r boot ) available only in isl6609a isl6609, isl6609a
3 fn9221.1 march 6, 2006 typical application - multiphase conv erter using isl6609 gate drivers +5v boot ugate phase lgate pwm en vcc v in +v core pgood vid fs/en gnd isen2 isen1 pwm2 pwm1 vsen pwm fb vcc +5v comp isl6609 control +5v (isl63xx (optional) or isl65xx) r ugph is required for special power sequencing applications r ugph (see application information section on page 8) +5v boot ugate phase lgate pwm en vcc v in isl6609 r ugph isl6609, isl6609a
4 fn9221.1 march 6, 2006 absolute maximum rati ngs thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v input voltage (v en , v pwm ) . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v boot voltage (v boot-gnd ). . . -0.3v to 25v (dc) or 36v (<200ns) boot to phase voltage (v boot-phase ) . . . . . . -0.3v to 7v (dc) -0.3v to 9v (<10ns) phase voltage . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 15v (dc) gnd -8v (<20ns pulse width, 10 j) to 30v (<100ns) ugate voltage . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot v phase - 5v (<20ns pulse width, 10 j) to v boot lgate voltage . . . . . . . . . . . . . . . gnd - 0.3v (dc) to vcc + 0.3v gnd - 2.5v (<20ns pulse width, 5 j) to vcc + 0.3v ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to 125c hbm esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kv recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to 100c maximum operating junction temperature . . . . . . . . . . . . . . 125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% thermal resistance (notes 1, 2, 3) ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 110 n/a qfn package (notes 2, 3). . . . . . . . . . 95 36 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. 3. jc , ?case temperature? location is at the center of the package underside exposed pad. see tech brief tb379 for details. electrical specifications these specifications apply for t a = -40c to 100c, unless otherwise noted parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc pwm pin floating, v vcc = 5v - 132 - a por rising -3.44.2 por falling 2.2 3.0 - hysteresis - 400 - mv pwm input sinking impedance r pwm_snk 2.75 4 5.5 k ? source impedance r pwm_src 3 4.25 5.75 k ? three-state rising threshold v vcc = 5v (100mv hysteresis) - 1.70 2.00 v three-state falling threshold v vcc = 5v (100mv hysteresis) 3.10 3.41 - v three-state shutdown holdoff time t tsshd t pdlu or t pdll + gate falling time - 20 - ns en input en low threshold 1.0 1.3 - v en high threshold -1.62.0v switching time (see figure 1 on page 6) ugate rise time (note 4) t ru v vcc = 5v, 3nf load - 8.0 - ns lgate rise time (note 4) t rl v vcc = 5v, 3nf load - 8.0 - ns ugate fall time (note 4) t fu v vcc = 5v, 3nf load - 8.0 - ns lgate fall time (note 4) t fl v vcc = 5v, 3nf load - 4.0 - ns ugate turn-off propagation delay t pdlu v vcc = 5v, outputs unloaded - 18 - ns lgate turn-off propagation delay t pdll v vcc = 5v, outputs unloaded - 25 - ns isl6609, isl6609a
5 fn9221.1 march 6, 2006 functional pin description note: pin numbers refer to the soic package. check diagram for corresponding qfn pinout. ugate (pin 1) upper gate drive output. connect to gate of high-side n-channel power mosfet. a gate resistor is never recommended on this pin, as it interferes with the operation shoot-through protection circuitry. boot (pin 2) floating bootstrap supply pin for the upper gate drive. connect a bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor provides the charge used to turn on the upper mosfet. see the bootstrap considerations section for guidance in choosing the appropriate capacitor value. pwm (pin 3) the pwm signal is the control input for the driver. the pwm signal can enter three distinct states during operation, see the three-state pwm input section for further details. connect this pin to the pwm output of the controller. gnd (pin 4) ground pin. all signals are referenced to this node. lgate (pin 5) lower gate drive output. conn ect to gate of the low side n-channel power mosfet. a gate resistor is never recommended on this pin, as it interferes with the operation shoot-through protection circuitry. vcc (pin 6) connect this pin to a +5v bias supply. locally bypass with a high quality ceramic capacitor to ground. en (pin 7) enable input pin. connect this pin high to enable and low to disable the driver. phase (pin 8) connect this pin to the source of the upper mosfet. this pin provides the return path for the upper gate driver current. thermal pad (in qfn only) the metal pad underneath the cent er of the ic is a thermal substrate. the pcb ?thermal land? design for this exposed die pad should include vias that drop down and connect to one or more buried copper plane(s). this combination of vias for vertical heat escape and buried planes for heat spreading allows the qfn to achieve its full thermal potential. this pad should be either grounded or floating, and it should not be connected to other nodes. refer to tb389 for design guidelines. ugate turn-on propagation delay t pdhu v vcc = 5v, outputs unloaded - 18 - ns lgate turn-on propagation delay t pdhl v vcc = 5v, outputs unloaded - 23 - ns three-state to ug/lg rising propagation delay t pts v vcc = 5v, outputs unloaded - 20 - ns output upper drive source resistance r ug_src 250ma source current - 1.0 2.5 ? upper drive sink resistance r ug_snk 250ma sink current - 1.0 2.5 ? lower drive source resistance r lg_src 250ma source current - 1.0 2.5 ? lower drive sink resistance r lg_snk 250ma sink current - 0.4 1.0 ? note: 4. guaranteed by characterization. not 100% tested in production. electrical specifications these specifications apply for t a = -40c to 100c, unless otherwise noted (continued) parameter symbol test conditions min typ max units isl6609, isl6609a
6 fn9221.1 march 6, 2006 timing diagram operation and adaptive shoot-through protection designed for high speed switching, the isl6609/09a mosfet driver controls both high-si de and low-side n-channel fets from one externally provided pwm signal. a rising transition on pwm initiates the turn-off of the lower mosfet (see timing diagram). after a short propagation delay [t pdll ], the lower gate begins to fall. typical fall times [t fl ] are provided in the electrical specifications . adaptive shoot-through circuitry monitors the lgate voltage and turns on the upper gate following a short delay time [t pdhu ] after the lgate voltage drops below ~1v. the upper gate drive then begins to rise [t ru ] and the upper mosfet turns on. a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlu ] is encountered before the upper gate begins to fall [t fu ]. the adaptive shoot-through circuitry monitors the ugate-phase voltage and turns on the lower mosfet a short delay time, t pdhl , after the upper mosfet?s gate voltage drops below 1v. the lower gate then rises [t rl ], turning on the lower mosfet. these methods prevent both the lower and upper mosfets from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge char acteristics of the mosfets being used. this driver is optimized for vo ltage regulators with large step down ratio. the lower mosfet is usually sized larger compared to the upper mosfet because the lower mosfet conducts for a longer time during a switching period. the lower gate driver is therefore sized much larger to meet this applicatio n requirement. the 0.4 ? on-resistance and 4a sink current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate capacitor of the lower mosfet and help prevent shoot through caused by the self turn-on of the lower mosfet due to high dv/dt of the switching node. three-state pwm input a unique feature of the isl6609/ 09a is the adaptable three- state pwm input. once the pwm signal enters the shutdown window, either mosfet previously conducting is turned off. if the pwm signal remains within the shutdown window for longer than the gate turn-off propagation delay of the previously conducting mosf et, the output drivers are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. the pwm rising and falling thresholds outlined in the electrical specifications determine when the lower and upper gates are enabled. during normal operation in a typical application, the pwm rise and fall times through the shutdown window should not exceed either output?s turn-off propagation delay plus the mosfet gate discharge time to ~1v. abnormally long pwm signal transition times through the shutdown window will simply introduce additional dead time between turn off and turn on of the synchronous bridge?s mosfets. for optimal performance, no more than 100pf parasitic capacitive load should be present on the pwm line of isl6609/09a (assuming an intersil pwm controller is used). bootstrap considerations this driver features an inte rnal bootstrap diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the isl6609a?s internal pwm ugate lgate t pdll t pdhu t ru t pdlu t pdhl t rl 1v 2.5v t ru t fu t fl 1v t pts t tsshd t tsshd t pts figure 1. timing diagram isl6609, isl6609a
7 fn9221.1 march 6, 2006 bootstrap resistor is designed to reduce the overcharging of the bootstrap capacitor when exposed to excessively large negative voltage swing at the phase node. typically, such large negative excursions occur in high current applications that use d 2 -pak and d-pak mosfets or excessive layout parasitic inductance. the following equation helps select a proper bootstrap capacitor size: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the ? v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. as an example, suppose two irlr7821 fets are chosen as the upper mosfets. the gate charge, q g , from the data sheet is 10nc at 4.5v (v gs ) gate-source voltage. then the q gate is calculated to be 22nc at vcc level. we will assume a 200mv droop in drive voltage over the pwm cycle. we find that a bootstrap capacitance of at least 0.110 f is required. the next larger standard value capacitance is 0.22f. a good quality ceramic capacitor is recommended. power dissipation package power dissipation is mainly a function of the switching frequency (f sw ), the output dr ive impedance, the external gate resistance, and the selected mosfet?s internal gate resistance and total gate charge. calculating the power dissipation in the driver for a desired application is critical to ensure safe ope ration. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125c. the maximum allowable ic power dissipation for the so8 package is approximately 800mw at room temperature, while the power dissipation capacity in the qfn package, with an exposed heat escape pad, is slightly better. see layout considerations paragraph for thermal transfer improvement suggestions. when designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected mosfets. the total gate drive power losses due to the gate charge of mosf ets and the driver?s internal circuitry and their corresponding average driver current can be estimated with equations 2 and 3, respectively, where the gate charge (q g1 and q g2 ) is defined at a particular gate to source voltage (v gs1 and v gs2 ) in the corresponding mosfet datasheet; i q is the driver?s total quiescent current with no load at both drive outputs; n q1 and n q2 are number of upper and lower mosfets, respectively. the i q v cc product is the quiescent power of the driver without capacitive lo ad and is typically negligible. the total gate drive power losses are dissipated among the resistive components along the transition path. the drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (r g1 and r g2 , should be a short to avoid interfering with the operat ion shoot-through protection circuitry) and the internal gate resistors (r gi1 and r gi2 ) of mosfets. figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. the power dissipation on the driver can be roughly estimated as: c boot_cap q gate ? v boot_cap -------------------------------------- q gate q g1 vcc ? v gs1 ------------------------------- n q1 ? = (eq. 1) 50nc 20nc figure 2. bootstrap capacitance vs boot ripple voltage ? v boot (v) c boot_cap (f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc 1.8 2.0 p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 2) p qg_q1 q g1 vcc 2 ? v gs1 ---------------------------------- f sw ? n q1 ? = p qg_q2 q g2 vcc 2 ? v gs2 ---------------------------------- f sw ? n q2 ? = i dr q g1 uvcc n q1 ? ? v gs1 ----------------------------------------------------- - q g2 lvcc n q2 ? ? v gs2 ---------------------------------------------------- - + ?? ?? ?? f sw i q + ? = (eq. 3) p dr p dr_up p dr_low i q vcc ? ++ = (eq. 4) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 2 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext2 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = isl6609, isl6609a
8 fn9221.1 march 6, 2006 application information mosfet and driver selection the parasitic inductances of the pcb and of the power devices? packaging (both upper and lower mosfets) can cause serious ringing, exceeding absolute maximum rating of the devices. the negative ringing at the edges of the phase node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper mosfet driver. careful layout, proper selection of mosfets and packaging, as well as the proper driver can go a long way toward minimizing such unwanted stress. the selection of d 2 -pak, or d-pak packaged mosfets, is a much better match (for the reasons discussed) for the isl6609a. low-profile mosfets, such as direct fets and multi-source leads devices (so-8, lfpak, powerpak), have low parasitic lead inductances and can be driven by either isl6609 or isl6609a (assuming proper layout design). the isl6609, missing the 3 ? integrated boot resistor, typically yields slig htly higher efficiency than the isl6609a. layout considerations a good layout helps reduce the ringing on the switching node (phase) and significantly lower the stress applied to the output drives. the following advice is meant to lead to an optimized layout: ? keep decoupling loops (vcc -gnd and boot-phase) as short as possible. ? minimize trace inductance, especially on low-impedance lines. all power traces (ugate, phase, lgate, gnd, vcc) should be short and wide, as much as possible. ? minimize the inductance of the phase node. ideally, the source of the upper and the drain of the lower mosfet should be as close as thermally allowable. ? minimize the current loop of the output and input power trains. short the source connection of the lower mosfet to ground as close to the transistor pin as feasible. input capacitors (especially cera mic decoupling) should be placed as close to the drain of upper and source of lower mosfets as possible. in addition, connecting the thermal pad of the qfn package to the power ground through a via, or placing a low noise copper plane underneath the soic part is recommended for high switching frequency, high current applications. this is to improve heat dissipation and allow the part to achieve its full thermal potential. upper mosfet self turn -on effects at startup should the driver have insufficient bias voltage applied, its outputs are floating. if the in put bus is energized at a high dv/dt rate while the driver out puts are floating, because of self-coupling via the internal c gd of the mosfet, the ugate could momentarily rise up to a level greater than the threshold voltage of the mosfet. this could potentially turn on the upper switch and result in damaging inrush energy. therefore, if such a sit uation (when input bus powered up before the bias of the controll er and driver is ready) could conceivably be encountered, it is a common practice to place a resistor (r ugph ) across the gate an d source of the upper mosfet to suppress the miller coupling effect. the value of the resistor depends mainly on the input voltage?s rate of rise, the c gd /c gs ratio, as well as the gate-source threshold of the upper mosfet. a higher dv/dt, a lower c ds /c gs ratio, and a lower gate-source threshold upper fet will require a smaller resistor to diminish the effect of the internal capacitive coupling. for most applications, a 5k to 10k ? resistor is typically suff icient, not affecting normal performance and efficiency. the coupling effect can be roughly estimated with the following equations, which assume a fixed linear input ramp and neglect the clamping effect of the body diode of the upper drive and the bootstrap capacitor. other parasitic components such as lead inductances and pcb capacitances are also not taken into account. these equations are provided for guidance purpose only. figure 3. typical upper-gate drive turn-on path figure 4. typical lower-gate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase vcc ugate vcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 gnd lgate isl6609, isl6609a
9 fn9221.1 march 6, 2006 therefore, the actual coupling effect should be examined using a very high impedance (10m ? or greater) probe to ensure a safe design margin. v gs_miller dv dt ------- rc rss 1e v ? ds dv dt ------- rc ? iss ? --------------------------------- - ? ?? ?? ?? ?? ?? ?? ?? = rr ugph r gi + = c rss c gd = c iss c gd c gs + = (eq. 5) figure 5. gate to source resistor to reduce upper mosfet miller coupling vin q upper d s g r gi r ugph boot du c ds c gs c gd dl phase vcc isl6609/a c boot ugate isl6609, isl6609a
10 fn9221.1 march 6, 2006 isl6609, isl6609a quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l8.3x3 8 lead quad flat no-lead plastic package (compliant to jedec mo-220veec issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 0.25 1.10 1.25 7, 8 e 3.00 bsc - e1 2.75 bsc 9 e2 0.25 1.10 1.25 7, 8 e 0.65 bsc - k0.25 - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n82 nd 2 3 ne 2 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9221.1 march 6, 2006 isl6609, isl6609a small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

▲Up To Search▲

Price & Availability of ISL6609IBZ

	To Download ISL6609IBZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .